1. Field of the Invention
The present invention relates to a voltage translator circuit and a semiconductor memory device, and more particularly, relates to a voltage translator circuit applicable to a driving circuit of a semiconductor memory device like a flash electrically erasable programmable read only memory (referred to as “flash EEPROM” hereinafter) and so forth.
2. Related Art
In some kinds of semiconductor memory devices, it is required to supply a plurality of different voltages to the word line depending on the operation mode of the memory device. In case of the flash EEPROM, for instance, the high electric potential (12V for instance) is applied to the word line in the data erasing operation and the data writing operation as well while the low electric potential (3.3V for example) is applied to the word line in the data reading operation. Accordingly, in the semiconductor memory devices similar to the above, it is needed to constitute such a driving circuit that the electric potential adaptable to different operation modes can be applied to the word line. Hereinafter, the expression “electric potential” will be written as “potential” in this specification just for simplification.
So far, there have been proposed various techniques for converting the voltage to be applied to the word line. For instance, it is known that the Japanese Patent Publication No. 10-149,693 discloses such voltage conversion technique. According to this technique as disclosed, the voltage translator circuit is set up between a row decoder and the word line.
FIG. 8 of the accompanying drawings is a circuit diagram showing a circuit identical to the voltage translator circuit as shown in FIG. 1 of the above Japanese Patent Publication.
Referring to FIG. 8, a buffer 811 and a NAND gate 812 constitute the final stage of the row decoder. From the NAND gate 812 is a signal with an ordinary voltage amplitude (high level=VDD, low level=GND) outputted. The voltage translator circuit 820 converts this signal into a signal with a large voltage amplitude (high level=VX, low level=VXGND) and supplies the converted to a plurality of predetermined word lines, which will be referred to as “the word line WL” hereinafter, because they are designated, in a lump, by using a single reference sign “WL” in the related figures, that is, FIGS. 1, 7, 8 and 9.
The voltage translator circuit 820 is provided with a MOS transistor of the n-conductive type (referred to as “nMOS transistor” hereinafter) 821 for pulling down the potential of the word line WL to the potential VXGND and a MOS transistor of the p-conductive type (referred to as “pMOS transistor” hereinafter) 822 for pulling up the potential of the word line WL to the potential VX. When the high level voltage (VDD) is outputted from a NAND gate 812, the nMOS transistor 821 is turned on while the pMOS transistor 822 is turned off, so that the potential of the word line WL is pulled down to the potential VXGND. On one hand, when the low level voltage (GND) is outputted from the NAND gate 812, the nMOS transistor 821 is turned off while the pMOS transistor 822 is turned on, so that the potential of the word line WL is pulled up to the high level potential VX. Furthermore, the voltage translator circuit 820 is provided with a pMOS transistor 823 for having the pMOS transistor 822 completely turned off when the potential of the word line WL is at a low level (VXGND). This pMOS transistor 823 is turned on as the nMOS transistor 821 is turned on and pulls up the gate potential of the pMOS transistor 822 up to the high level potential VX. In addition, the voltage translator circuit is provided an nMOS transistor 824 for preventing the drain potential VX of the pMOS transistor 823 from giving any ill effect to the row decoder.
FIG. 9 of the accompanying drawings is a circuit diagram showing a circuit identical to the voltage translator circuit as shown in FIG. 3 of the above Japanese Patent Publication. The voltage translator circuit shown in FIG. 9 is for improving the operation speed of the voltage translator circuit of FIG. 8, that is, for making it much faster.
In FIG. 9, a NOR gate 911 and a buffer 912 constitute the final stage of the row decoder. A voltage translator circuit 920 is provided with the same transistors as those 821 through 824 of the above voltage translator circuit 820 and is further provided with an nMOS transistor 921.
The NOR gate 911 having been changed from the low level (GND) to the high level, the nMOS transistor 921 is turned on and pulls down the gate potential of the pull-up transistor 822 to the low level (GND). With this, it become possible to turn on the pull-up transistor 822 at high speed, thus making it possible to pull up the potential of the word line WL to the high level (VX) at high speed.
Furthermore, in the voltage translator circuit 920, the gate of the nMOS transistor 824 is connected with the word line WL. With this, the pMOS transistor 823 having been turned on, the gate potential of the pull-up transistor 822 is set to be the potential that is a little higher than the output potential of the buffer 912. Because of this, when the output potential of the buffer 012 changes from the low level (GND) to the high level (VDD), the gate potential of the pull-up transistor 822 is increased at high speed, so that the turn-off operation of the pull-up transistor 822 is got speeded up, thus the pull-down of the potential of the word line WL being also got speeded up.
As described above, in case of the voltage translator circuit 920, the gate potential of the pull-up transistor 822 can be pulled down at high speed by providing the nMOS transistor 921. However, while the pMOS transistor 823 is turned on, the high voltage VX is applied between the source and drain of the pMOS transistor 921. Because of this, the pMOS transistor 921 has to be constituted such that it can withstand the high voltage applied thereto. That is, it is needed to elongate the length of the gate of the nMOS transistor 921 and at the same time, to increase the thickness of the gate oxide film of the same. Still further, as it is required to operate the nMOS transistor 921 at high speed, the nMOS transistor 921 can not help having a large dimension, that is, occupying a large circuit area on the semiconductor chip.
In addition, due to the provision of such a nMOS transistor 921 as occupies a large circuit area, the voltage translator circuit 920 comes to invite such a defect that the power consumption thereof increases. As described above, in the flash EEPROM, the high potential is applied to the word line WL in the data erasing operation and in the data writing operation as well while the low potential to the degree of the potential VDD is applied to the word line WL in the data reading operation. If the potential VX is very high, the pull-up transistor 822 operates at high speed. However, if the potential VX is low to the degree of the potential VDD, it takes a longer time for the gate potential of the pull-up transistor 822 to change from the low level to the high level. Because of this, the turn-off speed of the pull-up transistor 822 becomes slow. Consequently, if the potential VX is not sufficiently high but low, the period of on-time of both transistors 821 and 822 becomes longer, thus the penetration current flowing therethrough being increased.
For reasons as described in the above, there has been desired the appearance of such a voltage translator circuit that is able to operate at high speed, occupy a smaller circuit area, and consume a smaller electric power.
The present invention has been made in view of the shortcomings as described above, with regard to the prior art voltage translator circuit as described above. It is, therefore, a principal object of the invention is to provide a novel and improved voltage translator circuit capable of operating at high speed neither inviting enlargement of the circuit area nor increasing in the electric power consumption.